Integrated circuits (ICs) having multiple clock domains have come into wide use. The multiple clock domains allow hybrid or digital circuitry sharing the same substrate to be operated at different speeds asynchronously, i.e. not necessarily related to one another.
In almost every IC design, digital signals (signals communicating defined discrete logic levels, such as zero and one) are transmitted from an asynchronous domain (e.g., a separate clock domain) without requiring the transmitting and receiving domains to be synchronized with each other before transmission occurs. In such case, a flip-flop is provided to receive the digital signal. The flip-flop is able to capture the digital signal at any time. For this reason, flip-flops employed in the context of multiple clock domains are called synchronizers.
A drawback inherent in flip-flops is experienced when the digital signal's arrival time occurs during the synchronizer's setup or hold times (defined by the clock governing the domain in which the synchronizer lies). This causes a setup or hold violation, and the synchronizer is likely to enter a “metastable state” lying at between the defined discrete logic levels at a level that depends upon the characteristics of the electronic devices constituting the flip-flop. Until internal noise causes it to resolve to a stable state (namely a defined discrete logic level), the flip-flop dwells in the metastable state, and its output is unreliable. If the flip-flop fails to exit the metastable state in the given timing window (one cycle time for a two-stage synchronizer), it is regarded as having failed. The inverse of the rate at which a flip-flop fails is Mean Time Between Failure (MTBF).
One conventional approach to improving MTBF is to decrease the rate of the clock that governs the synchronizer's domain. However, the performance loss the entire domain suffers as a result is usually intolerable. A somewhat better conventional approach is to chain multiple synchronizers together to ensure that setup or hold violations are avoided in at least one synchronizer. Unfortunately, chained synchronizers require multiple clock cycles to propagate a signal to their ultimate output, which incurs latency.